1. Field of the Invention
The present invention relates to semiconductor devices and methods for manufacturing -semiconductor devices. The present invention particularly relates to a semiconductor device including a cylindrical capacitor and a method for manufacturing such a semiconductor device.
2. Description of the Related Art
In recent years, semiconductor devices with a large capacity have been increasingly demanded. Therefore, dynamic random access memories (DRAMs) with a large capacity, for example, a capacity of 1 Gbit, are in practical use.
Memory cells for DRAMs usually each include a gate transistor and a capacitor. The charge stored in the capacitor corresponds to information and is transferred with the transistor. The capacitor is connected to a diffusion layer electrode of the transistor and placed above the diffusion layer electrode or placed over a gate electrode and the diffusion layer electrode. The capacitor includes a lower electrode connected to the diffusion layer electrode, a commonly connected upper electrode, and a capacitor insulating layer placed therebetween.
A reduction in the size of gate transistors leads to a reduction in the area occupied by each capacitor. However, the capacitor needs to have a capacitance sufficient to ensure the operation of a memory because the charge stored in the capacitor corresponds to information. The following techniques are effective In achieving small-sized capacitors with a sufficient capacitance: the use of insulating films (dielectric films) with a small thickness, the use of capacitor insulating layers with a large dielectric constant, the use of capacitor electrodes with a large surface area, and the like.
That is, such thin dielectric films or high-surface area capacitors are used. In order to achieve the thin dielectric films, known dielectric films are reduced in thickness or a new material with a large dielectric constant is used. This leads to a decrease in reliability.
There are two solutions to achieve the high-surface area capacitors: one is to use cylindrical capacitors having a large aspect ratio and the other one is to use rough silicon layers or silicon layers having hemispherical silicon grains (hereinafter referred to as HSGs) protruding therefrom.
A HSG layer is formed as follows: an amorphous silicon layer for forming the lower electrode of a cylindrical capacitor is formed and then seeded by heat-treating the amorphous silicon layer in an atmosphere containing SiH4 or SiH6 and the resulting amorphous silicon layer is further heat-treated under high vacuum conditions, whereby HSGs are formed so as to protrude from the amorphous silicon layer. Silicon atoms provided by the seeding treatment are allowed to migrate to create crystal grains by the heat treatment.
When the amorphous silicon layer contains a large amount of an impurity such as phosphorus (P), the crystal grains cannot be sufficiently grown because the impurity inhibits the migration of the silicon atoms. In usual, the HSG layer is prepared by heat-treating the amorphous silicon layer having an impurity concentration of 1E20 to 2E20 atoms/cm3 or a smaller impurity concentration. If the obtained HSG layer has unsatisfactory electrical properties due to the low impurity concentration, the HSG layer is doped with P by heat-treating the HSG layer in an atmosphere containing PH3, whereby the impurity concentration of the HSG layer is increased. According to this technique, capacitors with a surface area about two times greater than that of known capacitors can be prepared; hence, small-sized memory cells with a desired capacity can be obtained. Higher advantages can be obtained if this technique is used in combination with the two techniques described above.
A reduction in the size of gate transistors leads to a reduction in the size of cylindrical capacitors; hence, the cylindrical capacitors have a small diameter and the distance between the cylindrical capacitors adjacent to each other is small. On the other hand, the HSG layer is readily peeled off. The peeled. HSG layer causes a short circuit between the cylindrical capacitors. This causes a reduction in the yield of memories. In order to prevent the short circuit which is occurs due to the peeling of the HSG, it is necessary to partly inhibit the growth of HSGs.
Japanese Unexamined Patent Application Publication Nos. 2000-196042, 2002-368133, and 2000-216346 (hereinafter referred to as Patent Documents 1, 2, and 3, respectively) disclose techniques for partly inhibiting HSGs from growing from cylindrical electrodes from which HSG layers are readily peeled off. According to Patent Documents 1 and 2, the HSGs protruding from the top ends of cylinder electrodes and the HSGs protruding from edges of box-shaped electrodes are prevented from growing, whereby short circuits are prevented from occurring between these electrodes. According to Patent Document 3, the HSGs placed protruding from the outer walls of cylindrical electrodes have a size different from that of the HSGs protruding from the inner walls thereof.
Japanese Unexamined Patent Application Publication No. 2001-196562 (hereinafter referred to as Patent Document 4) discloses a technique for preventing oxides in contact with cylinder walls from being exposed due to the removal of electrodes placed on the cylinder walls during the formation of HSGs. Japanese Unexamined Patent Application Publication No. 2002-222871 (hereinafter referred to as Patent Document 5) discloses a technique for reducing process cost and increasing throughput by forming HSGs in one step. Japanese Unexamined Patent Application Publication No. 2002-334940 (hereinafter referred to as Patent Document 6) discloses a technique for reducing the resistance of a concave capacitor having an inner wall with HSGs by directly connecting a contact plug to a metal wire.
In the above known techniques, the HSGs are formed in one step, the resistance of the capacitor is reduced, a short circuit is prevented from occurring due to the peeled HSG layer, or the adjacent cylindrical capacitors are prevented from being short-circuited. Methods for manufacturing small-sized capacitors for DRAMs and configurations of such capacitors are problematic as described below.
In order to increase the integration density of memory cells, holes are formed by etching so as to have a high aspect ratio. Such holes have lower zones having a diameter less than that of upper zones thereof. With reference to FIG. 23A, a mask insulating layer 33 and a second interlayer insulating layer 34 are arranged on a first interlayer insulating layer 31 including contact plugs 32. Capacitor holes 35, formed by lithography, for forming cylindrical capacitors extend through the mask insulating layer 33 and the second interlayer insulating layer 34. Each capacitor hole 35 has an top opening, represented by a-a′, having a diameter equal to the design value and lower zones, represented by b-b′, c-c′, or d-d′, each having a diameter different from the design value when the capacitor holes 35 are formed by lithography.
The diameter of the top opening a-a′ is the same as the design value. However, the upper zone b-b′ located below the top opening a-a′ has a diameter greater than that of the top opening a-a′ and the lower zone c-c′ located below the upper zone b-b′ has a diameter less than that of the upper zone b-b′, the lower zone C-C′ is tapered toward its bottom. And the capacitor hole 35 has a so-called bowing shape in cross section. For current high-capacity memories having holes with an aspect ratio of ten or more, lower regions of the holes are hard to etch because etching gas is not sufficiently supplied to the lower regions. Therefore, there is a problem that the diameter of the lower regions becomes small.
The capacitor hole 35 needs to be connected to each contact plug 32 placed thereunder. The bottom of the capacitor hole 25 is in contact with the mask insulating layer 33, which is therefore referred to as an etching stopper. When the mask insulating layer 33 is etched, the first interlayer insulating layer 31 is partly etched if the capacitor hole 35 is misaligned with the contact plug 32. Therefore, there is a problem in that the lower zone d-d′ of the capacitor hole 35 that is in contact with a side face of the contact plug 32 has a size less than that of other zones That is, in the capacitor hole 35, tie lower zone c-c′ has a diameter less than its design value and the lower zone d-d′ has a size less than its design value.
A silicon layer 36 for forming cylindrical lower electrodes for capacitors is formed over formed on the walls and bottoms of the capacitor holes 35 having the above shape. The silicon layer 36 is treated, whereby the lower electrodes having HSGs 37 are prepared. A capacitor insulating layer 38 is then formed so as to cover the HSGs 37. The HSGs 37 are densely arranged or are in contact with each other at the lower zone of the lower electrodes. The lower zone of the lower electrodes has a size less than its design value. For example, the lower zone is the bottoms of hole, the lower zone d-d′ and the lower zone c-c′. Since the capacitor Insulating layer 38 is not uniformly grown on the HGGs 37 densely arranged the capacitor insulating layer 38 is not uniform in thickness and therefore has thin sections.
Since the HSGs 37 protrude from the lower electrodes having narrow regions with sizes less than their design values as shown in FIG. 23B, the HSGs 37 protruding from a circumferential zone of the inner wall of each lower electrodes are in contact with each other if these HSGs 37 have a diameter greater than half of the diameter of the circumferential zone. Narrow spaces are present between the HSGs 37 in contact with each other. Since reactive gas for forming the capacitor insulating layer 38 can hardly be introduced into the narrow spaces, the step coverage of the capacitor insulating layer 38 is insufficient, hence, the capacitor insulating layer 38 has such thin sections. Since an oxidative species such as oxygen is exhausted in the narrow spaces during the oxidation of the capacitor insulating layer 38, the capacitor insulating layer 38 cannot be sufficiently oxidized. That is, the reactive gas in the narrow spaces is rarefied because the reactive gas is not sufficiently supplied to the narrow spaces.
When high electric fields are applied to the thin sections of the capacitor insulating layer 38, currents leak from the thin sections. A reduction in the thickness of the capacitor insulating layer 38 causes a decrease in the dielectric strength thereof. Although the capacitor insulating layer 38 is usually improved in dielectric strength by oxidation, there is a problem in that the capacitor insulating layer 38 has low dielectric strength because the oxidative species is insufficiently supplied to the narrow spaces.